Error Rate Failed Threshold
? Logical/Transport Layer Error Detect CSR defined in Section 126.96.36.199
? Logical/Transport Layer Error Enable CSR defined in Section 188.8.131.52
? Logical/Transport Layer Capture CSRs defined in Section 184.108.40.206 to Section 220.127.116.11
Logical/Transport Error Detect, Enable and Capture CSRs
当 error 发生时：
Error Detect 会被 set
如果是 “Error Enable”（Error Enable CSR）， 那么 Error Detect CSR 会被lock
error info 会被保存到 Capture registers
Software shall write the Logical/Transport Detect register with all logic 0s to clear the error detect bits or a corresponding enable bit to unlock the register.
Message Passing Error Detection
是要求 sender 和 receiver 同时要有 error check 的 特殊传输。
sender 方有个 timeout 值（Port Response Time-out Control CSR）， receiver 方有个类似的 counter
System Software Notification of Error
System Software 可以通过两种途径知道发生了错误。（1）是中断，但是规范无定义；（2）是 Maintenance port-write
Maintenance port-write 是由某个 device 发送给 system host（由 Port-write Target deviceID CSR 指定）
sending device sets the Port-write Pending status bit in the Port n Error and Status CSR.
A 16 byte data payload of the Maintenance Port-write packet contains the contents of several CSRs, the port on the device that encountered the error condition (for port-based errors), and some optional implementation specific additional information
Component Tag CSR ----- uniquely identify the reporting device within the system.
Port ID field
Port n Error Detect CSR
Logical/Transport Layer Error Detect CSR
Mechanisms for Software Debug
The Logical/Transport Layer Error Detect register and the Logical/Transport Layer Error Capture registers are writable by software to allow software debug of the system error recovery mechanisms.
For software debug, software must write the Logical/Transport Layer Error capture registers with the desired address and device
id information then write the Logical/Transport Layer Error Detect register to set an error bit and lock the registers.
When an error detect bit is set, the hardware will inform the system software of the error using its standard error reporting mechanism.
After the error has been reported, the system software may read and clear registers as necessary to complete its error handling protocol testing.
The Port n Error Detect register and the Port n Error Capture registers are also writable by software to allow software debug of the system error recovery and thresholding mechanism.
For debug, software must write the Port n Attributes Error Capture CSR to set the Capture Valid Info bit and then the packet/control symbol
information in the other capture registers.
Each write of a non-zero value to the Port n Error Detect CSR shall cause the Error Rate Counter to increment if the corresponding error bit is enabled in the Port n Error Rate Enable CSR.
When a threshold is reached, the hardware will inform the system software of the error using its standard error reporting mechanism.
After the error has been reported, the system software may read and clear registers as necessary to complete its error handling protocol