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RapidIO Error Management  

2012-02-07 11:25:35|  分类: 默认分类 |  标签: |举报 |字号 订阅

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  • Physical Layer Extensions
    1. Related registers(CSRs)
      1. ? (Extensions to the) Port n Control CSR                              defined in Section 2.2
        ? (Extensions to the) Port n Error and Status CSR                 defined in Section 2.2
        ? Port-write Target deviceID CSR                                       defined in Section 2.3.2.8
        ? Port n Error Detect CSR                                                 defined in Section 2.3.2.10
        ? Port n Error Rate Enable CSR                                          defined in Section 2.3.2.11
        ? Port n Attributes Capture CSR                                         defined in Section 2.3.2.12
        ? Port n Packet/Control Symbol Capture 0 CSR                      defined in Section 2.3.2.13
        ? Port n Packet Capture 1-3 CSRs                                      defined in Section 2.3.2.14 through Section 2.3.2.16
        ? Port n Error Rate CSR                                                    defined in Section 2.3.2.17
        ? Port n Error Rate Threshold CSR                                      defined in Section 2.3.2.18
    2. Port Error Detect, Enable and Capture CSRs
      1. 配置
        1. Port n Error Rate Enable CSR  控制那些类型的错误发生时,error  rate counter 的值会增加。
        2. 当 CVI (Capture Valid Info status bit, 在Port n Error Capture Attributes CSR 中 )  为0 时,下一个需要capture 的错误的相关信息将被保存到 Port n Error Capture CSRs ;在保存后,CVI 将被设为  1,那么  error capture registers 就被锁定(不能再保存新的错误信息)
      2. 使用
        1. 在发生错误时, Port n Error Capture Attributes CSR 中的 IT(Info Type) 和 ET(Error Type) 域将被更新
        2. capture CSRs 中可以保存:
          1. packet header  的话, ————  16 bytes(4 words)
          2. control symbol 的话, ————   4 bytes    
          3. 长度小于  16 bytes 的 packet,将会整个 packet 保存下来。
        3. CVI 被设为 1 后,后续的 错误信息 将不会被写入  Port n Error Capture CSRs  Port n Error Capture Attributes CSR  ;除非软件把 CVI 改成  0
        4. Port n Error Detect CSR  不会被锁定,所以后续错误信息会被继续写入该 register 中。该 register 显示了错误的类型。
    3. Error Reporting Thresholds
      1. Error Rate Degraded Threshold
        1. 如果  Error Rate Counter(在Port n Error Rate )   >=   Error Rate Degraded Threshold,那么:
          1. cause the error reporting logic to set the Output Degraded-encountered bit in the Port n Error and Status CSR
          2. notify the system software
      2. Error Rate Failed Threshold

        1. 如果  Error Rate Counter(在Port n Error Rate )   >=    Error Rate Failed Threshold,那么:
          1. cause the error reporting logic to set the Output Failed-encountered bit in the Port n Error and Status CSR
          2. notify the system software
    4. Packet Timeout Mechanism in a Switch Device
      1. If  "packet stay time"     >  Time-to-Live (in "Packet Time-to-live CSR"),
        1. packet dropped
        2. Output Packet-Dropped bit shall be set in the Port n Error and Status CSR
  • Logical and Transport Layer Extensions
    1. Related registers(CSRs)  

      1. ? Logical/Transport Layer Error Detect CSR defined in Section 2.3.2.2
        ? Logical/Transport Layer Error Enable CSR defined in Section 2.3.2.3
        ? Logical/Transport Layer Capture CSRs defined in Section 2.3.2.4 to Section 2.3.2.7

    2. Logical/Transport Error Detect, Enable and Capture CSRs

      1. 当 error 发生时:

        1. Error Detect   会被 set

        2. 如果是 “Error Enable”(Error Enable CSR), 那么 Error Detect CSR 会被lock

        3. error info 会被保存到     Capture registers

      2. error clear

        1. Software shall write the Logical/Transport Detect register with all logic 0s to clear the error detect bits or a corresponding enable bit to unlock the register.

    3. Message Passing Error Detection

      1.  是要求 sender 和 receiver 同时要有 error check 的 特殊传输。

      2. sender 方有个 timeout 值(Port Response Time-out Control CSR), receiver 方有个类似的 counter

  •  System Software Notification of Error

    1. System Software 可以通过两种途径知道发生了错误。(1)是中断,但是规范无定义;(2)是 Maintenance port-write

    2. Maintenance port-write 是由某个 device 发送给 system host(由 Port-write Target deviceID CSR 指定)

    3. Maintenance port-write

      1. sending device sets the Port-write Pending status bit in the Port n Error and Status CSR.

      2. A 16 byte data payload of the Maintenance Port-write packet contains the contents of several CSRs, the port on the device that encountered the error condition (for port-based errors), and some optional implementation specific additional information

      3. Payload info

        1. Component Tag CSR        -----    uniquely identify the reporting device within the system.

        2. Port ID field

        3. Port n Error Detect CSR

        4. Logical/Transport Layer Error Detect CSR

  • Mechanisms for Software Debug

    1. The Logical/Transport Layer Error Detect register and the Logical/Transport Layer Error Capture registers are writable by software to allow software debug of the system error recovery mechanisms.

    2. For software debug, software must write the Logical/Transport Layer Error capture registers with the desired address and device
      id information then write the Logical/Transport Layer Error Detect register to set an error bit and lock the registers.

    3. When an error detect bit is set, the hardware will inform the system software of the error using its standard error reporting mechanism.

    4. After the error has been reported, the system software may read and clear registers as necessary to complete its error handling protocol testing.

    5.  

    6. The Port n Error Detect register and the Port n Error Capture registers are also writable by software to allow software debug of the system error recovery and thresholding mechanism.

    7. For debug, software must write the Port n Attributes Error Capture CSR to set the Capture Valid Info bit and then the packet/control symbol
      information in the other capture registers.

    8. Each write of a non-zero value to the Port n Error Detect CSR shall cause the Error Rate Counter to increment if the corresponding error bit is enabled in the Port n Error Rate Enable CSR.

    9. When a threshold is reached, the hardware will inform the system software of the error using its standard error reporting mechanism.

    10. After the error has been reported, the system software may read and clear registers as necessary to complete its error handling protocol

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