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Raw NAND ECC  

2012-07-12 14:51:55|  分类: 默认分类 |  标签: |举报 |字号 订阅

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Introduction

The OMAP35x, AM35x, and AM/DM37x device's General Purpose Memory Controller (GPMC) support ECC detection only.  The OMAP35x supports both 1 and 8 bit detection while the AM35x (ES1.1 or higher) and the AM37x devices support 1, 4, and 8 bit detection.  With NAND Flash manufacturers moving to smaller process technologies, they are now requiring 4b ECC correction and will eventually move to higher ECC requirements. 

The following table outlines both the hardware and software detection and error correction capabilities available in the OMAP35x, AM35x, and AM/DM37x devices.

ECC support by OMAP device


GPMC (Hardware) Boot ROM Code (Fixed Software) Proposed Driver Solution (Software) 

Error Detection Error Correction Error Correction Error Correction

1b 4b 8b 1b 4b 8b 1b 4b 8b 4b 8b
OMAP35x YES NO YES NO NO NO YES NO NO NO YES
AM35x YES YES  YES NO NO NO YES NO NO YES YES
AM/DM37x YES YES  YES NO NO NO YES NO NO YES YES


Unlike OMAP35x/AM35x devices, DM/OMAPL13x/C674x/AM1xxx doesn't have GPMC or ECC support in ROM bootloader firmware. These device's EMIF hardware supports detection and correction for most of the devices (the ROM bootloader uses EMIF HW to support ECC). Please see for details.

What is ECC

An Error correcting code (ECC) is redundant data added to the original data. In event of errors, the combined data allows the recovery of the original data. The number of errors that can be recovered depends on the algorithm used.  Wikipedia article for more details on ECC.


Why is ECC required for NANDs?

Data stored in NANDs can get corrupted (randomly). There is an upper limit on the number of error per byte depending on the NAND process and the technology. SLC NANDs have less ECC requirements than MLC NANDs. The NAND datasheet gives the ECC requirement for the NAND device. For SLC NANDs, 1/4bits per 512 bytes are common currently. For MLC, devices with 4/8/16 bits per 512 bytes ECC requirements are in the market. 

 

What are the various algorithms and the differences used to implement ECC?


The various algorithms used in TI ECC hardware are:

  1. Hamming: For 1 bit
  2. Reed Solomon: For up to 4 bits of
  3. BCH : For more than 4 bits



Where is ECC stored in the NANDs?

Extra memory (called the "spare memory area" or "spare bytes region") is provided at the end of each page in NAND which could be used to store the ECC. This area is similar to the main page and is susceptible to the same errors. For the present explanation, assume that the page size is 2048 bytes and the ECC requirements are 4 bits per 512 bytes. Let's assume that the algorithm generates 16 bytes of redundant data per 512 bytes. For 2048 bytes page, 64 bytes of redundant data will be generated. (In current TI devices, the ECC data is generated for every 512 bytes)

There are two ways to store the redundant data:

  1. After every 512 bytes of data. This will cause some original data to be stored in the spare area. In RBL terminology, this is called "compatible mode".
  2. Completely within the spare memory area. Here, the original data is stored in the page followed by all of the redundant data for that page together. This is called "non-compatible mode".




Does ECC have to be calculated on a 512-byte data chunk?

TI device's hardware ECC implementation calculates ECC on 512 byte data chunks. As page size is always a multiple of 512, this gives a generic way to calculate the whole page ECC in parts and still reuse the same IP for various size NAND devices. However, from an ECC algorithm perspective, larger page size ECC can be calculated in one go.



Is it possible to use any ECC algorithm for any NAND?

Assuming software ECC and enough spare bytes, any ECC algorithm can be used. The NAND device is oblivious to the ECC algorithm used to correct bit errors.



What will happen if an 8-bit ECC NAND is used with our 4-bit ECC capable devices?


In this scenario, if more than 4 errors are detected, the errors can't be corrected. This can have serious consequences including boot failure. It is advisable to keep correcting the ECC errors in the designated read-only/boot sections of the NAND to reduce the chances of boot failure.



What is required to support 4b/8b ECC NAND devices?

ECC Correction

  • The OMAP35x, AM35x, and AM/DM37x devices do not support 4b or 8b correction in hardware, however, they do support 1b, 4b (not OMAP35x), and 8b hardware detection.  This requires for error correction to be done in software.


Boot Support

  • Currently the OMAP35x, AM35x, and AM/DM37x devices support only 1b error correction in the ROM for NAND Boot. However, many of the devices requiring 4- or 8-bit ECC have specified that the first block can be used with 1-bit ECC for a certain number of program erases cycles, e.g. 1000.



Software Performance:

Raw perfromance testing of the Software ECC correction algorithm was done on the AM37x EVM.  Below are the results of the test with artificially inserted errors.

  • 1-bit correction mode: 120 timer ticks or 4.61us to correct 1 error
  • 4-bit correction mode: 234,000 timer ticks or 9.00ms to correct 1 error with no meaningful performance difference when correcting 2 to 4 errors
  • 8-bit correction mode: 244,000 time ticks or 9.38ms to correct 1 error with no meaningful performance difference when correcting 2 to 8 errors



What are the options?

If you are planning a new design, with any of the above mentioned devices, you can utilize any of the options below.  For simplicity, we recommend the "eMMC/eSD NAND option".   For existing designs, choose the option below that best suits your application.


Use a NAND device that only requires 1 bit ECC

  • Some of the NAND Flash manufacturers are ending production of their NAND that only require 1 bit correction, but there are other manufacturers that do not have a current plan to EOL their 1 bit ECC devices. 
  • Hynix is one NAND manufacturer that currently continues to support 1b ECC NAND devices and is utilized on the AM37x EVM (TMDXEVM3715).


Boot with 1 bit ECC correction and run with NAND 4b correction in NAND flash

  • Some of the NAND Flash providers have started producing NAND devices with built in or on-die ECC for detection and correction.
  • For some of the NANDs, the built in ECC correction defaults to an "off state" upon power-on of the NAND device.
  • The NAND flash is specified such that the first block only requires 1-bit ECC correction.

At boot time, ROM Code will use 1 bit ECC algorithm to boot from the NAND device.

  • The ECC in the device (OMAP35x,AM35x,AM/DM37x) must then be disabled after boot (ie in XLOADER for example)
  • Then the built-in ECC in NAND device can be enabled (ie again in XLOADER)

Note:

If the device (OMAP35x, AM35x, AM/DM37x) has a warm reset the ROM code will startover and use 1b ECC correction, but because the NAND has the on-die ECC enabled there will be a conflict in the spare area for the ECC data because the ROM code spare area mapping and the NAND on-die mapping overlap.  The only way to disable the on-die ECC once it is enabled is to send a command to disable it, or to power cycle it.  Because of this the system will either fail to boot because the ROM code will try to correct the "errors" that it sees from the conflicting data, or it will boot because there are too many errors so it will just send the raw data without correcting. 

One option is for the system to cycle the power on the NAND when the PMIC receives the warm reset.  This will allow the NAND to go back to the on-die ECC off state and the system will boot as normal.

Note:

Precautions should be taken to ensure the ECC area doesn't conflict with the Flash File System area.


Boot with 1 bit ECC correction and run with 4b/8b correction in software

  • Some NAND providers are providing devices which guarantee that the 1st block only requires 1 bit correction.  Because the OMAP35x, AM35x, and AM/DM37x devices support 1b correction in ROM, booting can be done from the NAND device. After boot is complete, software ECC correction should be utilized.


eMMC/eSD NAND

  • Managed NAND has built in ECC and is connected via the MMC/SD interface. Because this interface has built-in ECC and is connected through the MMC/SD, the issues with the GPMC 4b/8b correction are not relevant. Memories compatible to MMC 4.2 and SD 2.1 will work seamlessly with these processors.
  • The Following managed NAND devices have been tested with OMAP35x, AM35x, and AM/DM37x devices:
Sandisk – SDIN2C2
Samsung – KMAFN0000M-S998


OneNAND

  • OneNAND has hardware ECC built in which eliminates the need for error correction to be done by the GPMC.
  • OneNAND is Interfaced through the GPMC as a muxed NOR flash device.  

Note: OneNAND devices is offered by samsung e.g. KFN8G16Q4M-AEB10


(AM35x only) Secondary Boot from SPI EEPROM

  • Boot from another type of device like NOR or SPI and then continue using NAND with 4b/8b ECC software correction.
  • SPI boot only available for AM35x


Secure a lifetime buy for current NAND device or utilize a pin for pin compatible solution that supports 1 bit ECC

  • Customers with existing designs with NAND that is becoming EOL should make arrangements with their NAND suppliers to secure supply for the lifetime of their product(s) or utilize one of the above options. 
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