The OMAP35x, AM35x, and AM/DM37x device's General Purpose Memory Controller (GPMC) support ECC detection only. The OMAP35x supports both 1 and 8 bit detection while the AM35x (ES1.1 or higher) and the AM37x devices support 1, 4, and 8 bit detection. With NAND Flash manufacturers moving to smaller process technologies, they are now requiring 4b ECC correction and will eventually move to higher ECC requirements.
The following table outlines both the hardware and software detection and error correction capabilities available in the OMAP35x, AM35x, and AM/DM37x devices.
|GPMC (Hardware)||Boot ROM Code (Fixed Software)||Proposed Driver Solution (Software)|
|Error Detection||Error Correction||Error Correction||Error Correction|
Unlike OMAP35x/AM35x devices, DM/OMAPL13x/C674x/AM1xxx doesn't have GPMC or ECC support in ROM bootloader firmware. These device's EMIF hardware supports detection and correction for most of the devices (the ROM bootloader uses EMIF HW to support ECC). Please see for details.
An Error correcting code (ECC) is redundant data added to the original data. In event of errors, the combined data allows the recovery of the original data. The number of errors that can be recovered depends on the algorithm used. Wikipedia article for more details on ECC.
Data stored in NANDs can get corrupted (randomly). There is an upper limit on the number of error per byte depending on the NAND process and the technology. SLC NANDs have less ECC requirements than MLC NANDs. The NAND datasheet gives the ECC requirement for the NAND device. For SLC NANDs, 1/4bits per 512 bytes are common currently. For MLC, devices with 4/8/16 bits per 512 bytes ECC requirements are in the market.
The various algorithms used in TI ECC hardware are:
Extra memory (called the "spare memory area" or "spare bytes region") is provided at the end of each page in NAND which could be used to store the ECC. This area is similar to the main page and is susceptible to the same errors. For the present explanation, assume that the page size is 2048 bytes and the ECC requirements are 4 bits per 512 bytes. Let's assume that the algorithm generates 16 bytes of redundant data per 512 bytes. For 2048 bytes page, 64 bytes of redundant data will be generated. (In current TI devices, the ECC data is generated for every 512 bytes)
There are two ways to store the redundant data:
TI device's hardware ECC implementation calculates ECC on 512 byte data chunks. As page size is always a multiple of 512, this gives a generic way to calculate the whole page ECC in parts and still reuse the same IP for various size NAND devices. However, from an ECC algorithm perspective, larger page size ECC can be calculated in one go.
Assuming software ECC and enough spare bytes, any ECC algorithm can be used. The NAND device is oblivious to the ECC algorithm used to correct bit errors.
In this scenario, if more than 4 errors are detected, the errors can't be corrected. This can have serious consequences including boot failure. It is advisable to keep correcting the ECC errors in the designated read-only/boot sections of the NAND to reduce the chances of boot failure.
Raw perfromance testing of the Software ECC correction algorithm was done on the AM37x EVM. Below are the results of the test with artificially inserted errors.
If you are planning a new design, with any of the above mentioned devices, you can utilize any of the options below. For simplicity, we recommend the "eMMC/eSD NAND option". For existing designs, choose the option below that best suits your application.
At boot time, ROM Code will use 1 bit ECC algorithm to boot from the NAND device.
If the device (OMAP35x, AM35x, AM/DM37x) has a warm reset the ROM code will startover and use 1b ECC correction, but because the NAND has the on-die ECC enabled there will be a conflict in the spare area for the ECC data because the ROM code spare area mapping and the NAND on-die mapping overlap. The only way to disable the on-die ECC once it is enabled is to send a command to disable it, or to power cycle it. Because of this the system will either fail to boot because the ROM code will try to correct the "errors" that it sees from the conflicting data, or it will boot because there are too many errors so it will just send the raw data without correcting.
One option is for the system to cycle the power on the NAND when the PMIC receives the warm reset. This will allow the NAND to go back to the on-die ECC off state and the system will boot as normal.
Precautions should be taken to ensure the ECC area doesn't conflict with the Flash File System area.
Note: OneNAND devices is offered by samsung e.g. KFN8G16Q4M-AEB10