IPC (InterProcessor Communication) is a rather overused term. In general, it refers to synchronization/messaging between processors or even tasks. On Keystone devices (and earlier TI processors) there are also “IPC” registers, which provide a rudimentary core-to-core interrupt capability.
EDMA3 is a normal (though very flexible) DMA, which can be used for simple messaging schemes by using its Transfer Completion interrupts. So in this respect, EDMA3 can be used as an IPC module.
Multicore Navigator is a combination of a hardware Queue Manager Subsystem (a Queue Manager plus several dedicated firmware processors and other auxiliary pieces) plus a number of pktDMAs (Packet DMA) that are distributed around the device. The number of pktDMAs varies from device to device, but in Appleton (TCI6614) there are pktDMAs in these IP:
QMSS (infrastructure – a memory to memory pktDMA)
There are several ways that Navigator can be used as an IPC module:
- Queues can be polled, by multiple “slaves” if necessary.
- Special queues can trigger CP-INTC interrupts.
- QMSS INTD can be used independently to trigger interrupts.
- QM by itself can be used for zero-copy or shared memory messages.
- QM with Infrastructure pktDMA for point-to-point messages. Rx queues can be polled or interrupt driven.
- QM with Infrastructure pktDMA and Accumulator. Accumulator firmware performs Rx queue management in the background with interrupts to host.
So it is much more flexible than the IPC registers and EDMA3 combined.
Differences between EDMA3 and pktDMA:
EDMA3 is slightly faster.
pktDMA is more flexible.
pktDMA is unconcerned with data format or stride. It simply moves chunks of data.
pktDMA (and QM) handle atomicity issues.
pktDMA is easier to program and use, though it requires more initial setup than EDMA3.
There is a wider variety of ways to respond to pktDMA outputs (descriptors written to Rx queues).
pktDMA transfers can be chained from one to another.